Multi-channel testing architecture for high-speed eye-diagram using pin electronics and subsampling monobit reconstruction algorithms
Thomas Moon, Hyun Woo Choi, David C. Keezer, Abhijit Chatterjee · 2014
This paper proposes a new multi-channel testing architecture for high-speed eye-diagram. The proposed architecture reconstructs the eye-diagram of a multi-Gbps bit pattern with the combination of pin electronics and reconstruction algorithms. A scalability of the test system significantly increases in behalf of a monobit receiver and its designated reconstruction algorithm. A novel reconstruction algorithm using monobit receiver and subsampling clock enables the test system to monitor the signal quality in low-cost. The proposed architecture is implemented and demonstrated in a hardware prototype. Experiment with the hardware prototype shows that an eye-diagram of 3.2Gbps bit pattern can be reconstructed within sub-picosecond resolution by the proposed method with subsampling clock (below 100MHz).