Exploiting symbolic techniques for partial scan flip flop selection
Fulvio Corno, P. Prinetto, Matteo Sonza Reorda, Massimo Violante · 1998
Partial Scan techniques have been widely accepted as an effective solution to improve sequential ATPG performance while keeping acceptable area and per-formance overheads. Several techniques for flip-flop selection based on structural analysis have been pre-sented in the literature. In this paper, we first propose a new testability measure based on the analysis of the circuit State Transition Graph through symbolic tech-niques. We then describe a scan flip flop selection algo-rithm exploiting this measure. We resort to the identifi-cation of several circuit macros to address large se-quential circuits. When compared to other techniques, our approach shows good results, especially when it is used to optimize a set of flip-flops previously selected by means of structural analysis. 1.