A BIST method based on concurrent single-control testability of RTL data paths
K. Yamaguchi, Hiroyuki Wada, Toshimitsu Masuzawa, Hideo Fujiwara · 2002
This paper presents a new BIST (Built-In Self-Test) method for register transfer level data paths based on both hierarchical testing and a "test-per-clock" scheme. In the proposed method, test pattern generators and response analyzers are placed on primary inputs and primary outputs, and test patterns and test responses are transferred along paths in the data paths. This paper proposes a new testability for BIST, concurrent single-control testability, and presents a new BIST method based on the testability. The concurrent single-control testability is an extension of a previous single-control testability and has advantage that test application time becomes shorter because multiple combinational modules can be tested at the same time (i.e., concurrent testing). Our experimental results show that the proposed method reduces test application time without increasing so much hardware overhead compared with the previous method.