Hierarchical test generation using precomputed tests for modules
Brian T. Murray, John P. Hayes · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1990
A novel test generation technique for large circuits with high fault coverage requirements is described. The technique is particularly appropriate for circuits designed by silicon compilers. Circuit modules and signals are described at a high descriptive level. Test data for modules are described by predefined stimulus/response packages that are processed symbolically using techniques derived from artificial intelligence. The packages contain sequences of stimulus and response vectors which are propagated as units. Since many test vectors are processed simultaneously, a substantial increase in test generation speed can be achieved. A prototype test generator which uses the technique to generate tests for acyclic circuits has been implemented. Preliminary results from this program suggest that for circuits composed of datapath elements, speed improvements of three orders of magnitude over conventional techniques may be possible.>