RT-level ITC'99 benchmarks and first ATPG results
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero · IEEE Design & Test of Computers · 2000
New design flows require reducing work at the gate level and performing most activities before the synthesis step, including evaluation of testability of circuits. We propose a suite of RT-level benchmarks that help improve research in high-level ATPG tools. First results on the benchmarks obtained with our prototype tool show the feasibility of the approach.