A built-in self-repair design for RAMs with 2-D redundancy
Jin-Fu Li, J. C. Yeh, Rei-Fu Huang, Cheng‐Wen Wu · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2005
This brief presents a built-in self-repair (BISR) scheme for semiconductor memories with two-dimensional (2-D) redundancy structures, i.e., spare rows and spare columns. The BISR design is composed of a built-in self-test module and a built-in redundancy analysis (BIRA) module. The BIRA module executes the proposed RA algorithm for RAM with a 2-D redundancy structure. The BIRA module also serves as the reconfiguration unit in the normal mode. Experimental results show that a high repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories) is achieved with the BISR scheme. The BISR circuit has a low area overhead-about 4.6% for an 8 K /spl times/ 64 SRAM.