The cost and performance tradeoffs of buffered memories
A.V. Pohm, Om P. Agrawal, R.N. Monroe · Proceedings of the IEEE · 1975
An analysis of the performance enhancement achieved and the incremental costs accrued in buffering (using a cache memory) memory systems is made. Buffering is found to be cost-effective even for minicomputer memories. The study indicates that the flagged registered swap algorithm is superior to three other common algorithms used. It is shown that when jobs are switched, a substantial number of memory requests are required before the buffer fills and gives a high hit ratio. It is also shown that individuaIly buffered main-memory modules can be interleaved to achieve very high system performance.