Consequences of RAM Bitline Twisting for Test Coverage
I. Schanstra, A.J. van de Goor · 2003
Abstract: In order to reduce coupling effects between bitlines in static or dynamic RAMs, bitline twisting can be used in the design. For testing, however, this has consequences for the to-be-used data backgrounds. A generic twisting scheme is introduced and the involved fault models are identified. 1 Formal twisting notation Twisting can be defined as the local reordering of parallelrunning interconnect lines. It can be used for the bitline and/or wordline schemes of memories, or for busses in general [1-7]. Figure 1 shows a generic twisting scheme for a large number of interconnect lines that run from left to right. It is called a two-dimensional twisting scheme, because all lines run in a plane1. l lines