Simulation and analysis of a pipeline processor
Philip Emma, Joshua W. Knight, J. H. Pomerence, Thomas R. Puzak, R. N. Rechtschaffen · 1989
In this paper we describe a software simulator (a timer) that is used to model a wide range of pipeline processors. A set of performance equations is developed that allow a user to separate the performance of a processor into its infinite-cache and finite-cache performance values. We then use the timer to study the performance of two different machine organizations. Performance curves are presented that help a user compare the performance of each organization (in terms of MIPS and cycles per instruction) to the cycle time chosen to implement the design.