VLSI architecture prototyping of pipelined IIR digital filter
Mehboob Alam, Wael Maged Badawy · 2003
The paper presents a technique for VLSI prototyping pipelining IIR digital filters and offers a detail solution to single chip implementation. The proposed implementation scheme uses the GCLA (generalized cluster look ahead) technique with overflow avoidance to add further stability to the filter. The design using direct and pipelined architecture is implemented on Xilinx V50CS144 device of the Vertex family and optimal results for time were achieved.