FPGA implementation of a reconfigurable microprocessor
Jacob Davidson · 2002
The implementation of an 8-b reconfigurable microprocessor (RM) in a memory-based FPGA (field programmable gate array) device (XILINX) is described. The RM is designed as an 8-b microprocessor with a complete instruction set (41), hardware and software interrupts, and a 2-Kb addressing range (11-b address bus). The author presents the tradeoffs involved in designing the architecture, the design for performance issues, and the possibilities for future development.