Architectural rule checking for high-level synthesis
Jie Gong, Chih-Tung Chen, K. Kücükcakar · Design, Automation, and Test in Europe · 1998
Verifying an implementation produced from high-level synthesis is a challenging problem due to many complex design tasks involved in the design process. In this paper, we present an architectural rule checking approach for high-level design verification. This technique detects and locates various design errors and verifies both the consistency and correctness of an implementation. Besides describing different rule suites, we also report a working environment for the architectural rule checking. Finally, we highlight the value of the proposed approach with a real-life design.