A VLSI chip set for a multiprocessor workstation. I. An RISC microprocessor with coprocessor interface and support for symbolic processing
D.D. Lee, Shing I. Kong, M.D. Hill, George S. Taylor, David A. Hodges, Randy Howard Katz, David A. Patterson · IEEE Journal of Solid-State Circuits · 1989
A 40-70 MIPS multiprocessor workstation is considered. VLSI implementation of the central processing unit (CPU) chip, based on reduced instruction set computer (RISC) architecture and with support for LISP, is described. The 1.3-cm/sup 2/ CPU chip uses a direct-mapped 512-b on-chip instruction cache and 138 40-b registers organized in eight overlapping windows to achieve 10 MIPS per processor peak performance with a 10-MHz, four-phase clock.>