A high performance FPGA implementation of DES
M. McLoone, John V McCanny · 2002
FPGAs have proven to be very effective and efficient devices on which to implement encryption algorithms. They perform at much faster data-rates and provide better security than equivalent software implementations. They also provide more flexibility than ASIC implementations. This paper presents a high performance silicon intellectual property (IP) core for the data encryption standard (DES) encryption algorithm. The 16-stage pipelined DES design runs at an encryption rate of 3.87 Gbits/s using Xilinx Virtex FPGA technology making this the fastest single-chip DES FPGA implementation reported to date. This result is a factor 28 times faster than software implementations.