Test generation for current testing of bridging faults in CMOS VLSI circuits
T. Lee, Ibrahim N. Hajj · 2002
An efficient automatic test pattern generator for I/sub DDQ/ current testing of CMOS digital circuits is presented. The complete two-line bridging fault set is considered. Genetic algorithms are used to generate compact test sets. Experimental results for ISCAS85 and ISCAS89 benchmark circuits are presented.