Delay fault simulation of self-checking error checkers
Kanji Hirabayashi · 2002
A robustly-tested gate-delay fault model is proposed using 7-valued logic, and applied to the delay fault simulation of self-checking error checkers. The simulated results are compared with those obtained using either a nonrobustly-tested gate-delay fault model or a path-delay fault model. Experiments show that the robustly-tested gate-delay fault model gives the most pessimistic evaluation for delay test effectiveness. The CMOS pass transistor logic implementation of the self-checking error checkers is discussed.>