A multi-standard video decoder for high definition video applications
Cheng-An Chien, Chih-Da Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng · 2009
Through reducing 70% of external memory bandwidth and 60% of computational complexity, the proposed 252 Kgates/71 mW/0.13 um multi-standard (JPEG/MPEG-1/2/4/H.264) video decoder reduces 72% in gate count and 87% in power consumption as compared to the state-of-the-art design, when operating at 120 MHz for real-time HD1080 video decoding with single AHB-based SDR memory.