Automatic verification of scheduling results in high-level synthesis
Hans Eveking, Holger Hinrichsen, Gerd Ritter · 1999
A method for the fully automatic equivalence verification of a design before and after the scheduling step of high-level synthesis is presented.The technique is applicable to the results of advanced scheduling methods like AFAP and DLS, which work on cyclic control flows, as well as to pipelined designs.