Reducing the branch penalty by rearranging instructions in a double-width memory
Manolis G. H. Katevenis, Nestoras Tzartzanis · 1991
Article Free Access Share on Reducing the branch penalty by rearranging instructions in a double-width memory Authors: Manolis Katevenis View Profile , Nestoras Tzartzanis View Profile Authors Info & Claims ASPLOS IV: Proceedings of the fourth international conference on Architectural support for programming languages and operating systemsApril 1991 Pages 15–27https://doi.org/10.1145/106972.106977Published:01 April 1991Publication History 5citation533DownloadsMetricsTotal Citations5Total Downloads533Last 12 Months125Last 6 weeks20 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF