Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic
Gopal Chandra Paul, Sambhu Nath Pradhan, Ajit Pal, Bhargab B. Bhattacharya · 2006
Binary decision diagrams (BDDs) play an important role in the synthesis, verification, and testing of VLSI circuits. In this paper, we have proposed a new BDD-based synthesis technique using dual rail static differential cascode voltage switch with pass gate (DCVSPG) logic. The method yields around 22% reduction in number of MUX cells. Simulation result using SPICE on 180 nm technology with 1.5 volts supply shows, on an average, 65% reduction in power consumption for frequency ranging up to 1 GHz compared to the result with static CMOS logic. It is envisaged that the proposed approach is useful in realizing low-power circuits