TESTING OF SOC INTERCONNECTS USING EXTENDED IEEE 1500 STANDARD
Nafiseh Mousavian, Reza Nourmandi-Pour, Arash Ghorbannia Delavar · Journal of Circuits Systems and Computers · 2012
In this paper, we proposed BIST-based architecture to at-speed test of crosstalk faults for system-on-chip interconnects. This architecture includes IEEE 1500 wrapper enhanced cells intended for multiple victim test model test patterns generation and analysis test responses. One new instruction is used to control cells and test pattern generator controller in serial test access mechanism of the standard in order to fully comply with conventional IEEE 1500 standard.