Automatic test procedure generation from system specifications
Michael Karel Lindsey · 2003
Automated aids to generating test procedures for electronic systems from top-level system specifications are described. A five-phase design methodology which incorporates VHSIC description language, (VHDL) modeling allows concurrent development of complex systems and associated test procedures. The methodology proceeds in a top-down fashion, progressively adding design detail in each phase. A proprietary software tool combined with VHDL modeling allow test information to automatically migrate through each phase. This allows system implementation to be verified against the original top-level specification. This method of automated test procedure generation provides significant insight into system operation.>