A limit cycle suppressing arithmetic format for digital filters
Peter H. Bauer, K. Ralev · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · 1998
In this paper it is be shown that any digital filter with a stable transfer function can be implemented free of limit cycles, if block floating point arithmetic is used in conjunction with the so-called exponent saturation and flush-to-zero option. A certain system dependent minimum block mantissa length is required. Limit cycle suppression is achievable regardless of the structure and the quantization format. This format is simple to implement even on fixed point processors and offers high dynamic range.