High-speed I/sub DDQ/ measurement circuit
Kenji Isawa, Y. Hashimoto · 2002
The I/sub DDQ/ test is an effective means of testing CMOS ICs that contain a high level of integration. However, the test presents a practical disadvantage due to the low test rate of less than 50 kHz. A new circuit was designed in an attempt to realize a higher test rate. When evaluated by simulation at a target current level of 1 /spl mu/A, the new circuit demonstrated a potential test rate of 1 MHz in continuous testing.