IC implementation of a current-mode chaotic neuron
R. Herrera, Kanako Suyama, Yoshihiko Horio · 2002
An IC implementation of a new current-mode chaotic neuron is presented. The circuit mainly consists of CMOS inverters, which are used as transconductance amplifiers and nonlinear elements. The chip was fabricated using 1.2 /spl mu/m HP CMOS process. One neuron occupies only 0.0076 mm/sup 2/ which is smaller than a standard bonding pad. The circuit was tested at a clock frequency of 2 MHz.