FFT implementation on the TMS320C30
Panos E. Papamichalis · 2003
The implementation of several FFT (fast Fourier transform) algorithms on the TMS320C30, the third-generation device in the Texas Instruments family of digital signal processors is reported. The algorithms considered are the complex radix-2 and radix-4, and real-valued radix-2 FFT. The architecture and the instruction set of the TMS320C30 permit flexible and compact coding of the algorithms in assembly language while preserving close correspondence to a high-level language implementation. The efficiency of the architecture and the speed of the device (60 ns) make possible the realization of a 1024-point FFT in 3.75 ms (complex, radix-2), 3.04 ms (complex, radix-4), or 1.67 ms (real, radix-2).>