BitSNAP: Dynamic Significance Compression for a Low-Energy Sensor Network Asynchronous Processor
Virantha Ekanayake, Clinton W. Kelly, Rajit Manohar · 2005
We present a novel asynchronous processor architecture called BitSNAP that utilizes bit-serial datapaths with dynamic significance compression to yield extremely low-energy consumption. Based on the sensor network asynchronous processor (SNAP) ISA, BitSNAP can reduce datapath energy consumption by 50% over a comparable parallel-word processor, while still providing performance suited for powering low-energy sensor network nodes. In 180 nm CMOS, the processor is expected to run at between 6 and 54 MIPS while consuming 152 pJ/ins at 1.8 V and just 17 pJ/ins at 0.6 V.