A multiprocessor architecture for high speed network interconnections
Martina Zitterbart · 1989
A multiprocessor architecture suitable for the implementation of high-speed gateways is presented. It is based on a horizontal and vertical subdivision of communication systems. The resulting architecture consists of several receive and send pipelines, where every receive and send pipeline is associated with one subnetwork connected to the gateway. The pipeline stages are implemented on several processors which are combined into a processor unit. The internal structure of each processor unit is adapted to the protocol functions that are to be implemented on it. The architecture comprises pipeline structures and array structures and thus permits temporal parallelism as well as spatial parallelism.>