A memory efficient array architecture for real-time motion estimation
Vasily G. Moshnyaga, Kiichiro Tamaru · 2002
A new 2-D array architecture for real-time video picture motion estimation is presented. Due to incorporated concepts of video memory distribution and sharing, the architecture ensures feasible solutions for the HDTV picture format with lower memory requirements. It features minimal I/O pin count, 100% processor utilization and is quite suitable for VLSI implementation.