Design Of Low Power Parallel FIR Digital Filter Using Floating - Point Multiplier
Neelam Gathibandhe, Pradnya Pravin Zode, Yashwantrao Chavhan, Himalaya Vishva · 2013
The Finite impulse response (FIR) filter is used as a fundamental processing element in any Digital signal processing (DSP) system. This paper describe the technique of Algorithemic strength reduction which leads to a reduction in hardware complexity by exploiting substructure sharing(by reducing the number of multiplications and additions). This transformation is basically implemented for the reduction in silicon area or power consumption of Very large scale integration (VLSI) design or iteration period in a programmable digital signal processing (DSP) implementation. Here we will focus on implementation based on Field Programmable Gate Array (FPGAs) because many of the approaches are applicable to ASIC or custom VLSI application. The sub-modules has been written in Verilog HDL and they are synthesized and simulated using the Xilinx ISE targeted on Field programmable Gate Array (FPGA).