A Low-power Motion Compensation IP Core Design for MPEG-1/2/4 Video Decoding
Chih-Da Chien, H. J. Chen, Lin-Chieh Huang, Jiun-In Guo · 2005
The proposed IP core design design exploits an adder-based quarter-pixel filter optimized by data sharing for low cost consideration. This optimization reduces over 87% of hardware complexity as compared to the quarter-pixel filter in the existing design (Wang, J.X. et al. Proc. IEEE ASIC Conf., vol.2, p.942-5, 2003). In addition, we propose a low-power design technique called dynamic partially guarded computation (DPGC) to reduce the power consumption on pixel interpolation. After applying the DPGC, we obtain 60% reduction in the power consumption of the interpolation operations in the proposed design. Using a 0.18 /spl mu/m CMOS technology, the proposed design achieves real-time processing of MPEG-1/2/4 decoding on 4CIF video when operated at 54 MHz. In addition, the proposed design has been integrated into a MPEG-4 video decoder for system verification through a XILINX multimedia FPGA board.