An 80-Mb/s 0.18-μm CMOS analog min-sum iterative decoder for a (32,8,10) LDPC code
Saied Hemati, Amir H. Banihashemi, Calvin Plett · 2006
Analog current-mode circuits are presented for implementing min-sum (MS) iterative decoders, which are used for decoding low-density parity-check (LDPC) codes and turbo codes. While previously reported analog decoders rely on the exponential characteristics of bipolar or subthreshold MOS transistors, proposed circuits can also be used for designing strongly inverted CMOS analog decoders. A proof-of-concept 80-Mb/s CMOS MS decoder is designed and fabricated that consumes the least reported energy per bit and operates at least six times faster than previously reported CMOS analog decoders.