A proven methodology for designing one-million-gate ASICs
A.M. Rincon, M. Trick, T. S. Guzowski · 2002
This paper describes the methodology used to design a family of ASIC chips in the 400 K to one-million-gate range in a 0.5 micron technology. Working first-pass hardware was produced at an average clock speed of 100 MHz with over 99% testability. The methodology utilized a variety of third-party CAD tools from Synopsys and Cadence in combination with proprietary IBM tools.