Theoretical Evaluation of Simultaneous Multithreading Para Ilel Queue Processor Architecture
Hirotoshi Sasaki, Yoshitomo Okumura, Abderazek Ben Abdallah, Soichi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa · ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications · 2004
In this paper, we describe abstraction of Simultaneous Multithreading Parallel Queue Processor (SMT-PQP) architecture. SMT-PQP is based on the queue calculation model. SMT-PQP can provide both Instruction Level Parallelism (ILP) and Thread Level Parallelis m (TLP). Namely, it has the ability to offer an appropriate granularity of parallelism for all applications. As a result, SMT-PQP achieves high usability of calculation resources, it expands register resources and does not need to support a register renaming function. A theoretical evaluation of SMT-PQP is described.