An automatic testing technique for PLDs
A. Elsayed, Mohamed E. Elbably, Hatem EL-Bolok · 2003
The programmable logic devices (PLDs) are widely used in the hardware implementation of many designed circuits. Identifying the faulty row, which contains many configurable logic blocks (CLBs) was the aim of many researchers. A. new technique is proposed in this research. The main aim of the proposed technique concentrates on identifying the location of the faculty CLB in FPGA (field programmable gate array) chips.