An Optimized BIST Architecture for FPGA Look-Up Table Testing

Mahnaz Yarandi; Armin Alaghi; Zainalabedin Navabi

doi:https://doi.org/10.1109/isvlsi.2006.24

An Optimized BIST Architecture for FPGA Look-Up Table Testing

Mahnaz Yarandi, Armin Alaghi, Zainalabedin Navabi · 2006

This paper presents a complete BIST architecture for FPGA look-up tables. This architecture can detect multiple faults, and can be configured to detect a fault in as few as five LUTs. Unlike an earlier work, our method places the output response analyzer (ORA) within the FPGA.

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