IC performance prediction for test cost reduction
Jungran Lee, D.M.H. Walker, Linda S. Milor, Yeng Peng, Geoff Hill · 2003
This paper describes a methodology for building models predicting manufactured integrated circuit performances as a function of inline and wafer electrical test measurements. We show how these predictions can be used to predict the performance of an industrial microprocessor, and reduce the average number of speed bins that must be tested by 45%.