New bit-serial VLSI implementation of RNS FIR digital filters
Chin-Liang Wang · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 1994
A bit-serial hybrid VLSI architecture that consists of both table-look-up and conventional binary modules is proposed to implement FIR digital filters using the residue number system (RNS). The architecture is constructed based on a new theorem for performing the operation /spl alpha/+x/spl beta/ mod m without look-up tables, where m is a modulus in the RNS, /spl alpha/ and /spl beta/ are two numbers in module m, and x/spl isin/{0,1}. As compared to a bit-parallel hybrid realization method described recently, the proposed bit-serial one does not need to broadcast input data to the processing elements used and reduces the table-look-up memory in each module processor from (B+2/sup upper bound [log(2/N])-1)/spl middot/B/spl middot/2/sup 2B/ bits to B/spl middot/2/sup 2B/ bits, where B is the wordlength of each modulus and N is the number of filter coefficients. As a consequence, it can provide better performance in VLSI implementation for applications where large moduli and/or large filter orders are used.>