System-Level Specification Testing Of Wireless Transceivers
Arnab Halder, S. Bhattacharya, Abhijit Chatterjee · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2008
This paper presents an efficient system-level manufacturing test methodology for wireless transceiver systems. Conventional system-level testing procedures incur large test times and require the use of multiple test hardware configurations for measuring frequency and modulation-domain performance specifications, e.g., system-gain, nonlinearity, noise-figure, channel power, adjacent-channel power-ratio, error vector magnitude, modulation signal-to-noise ratio and bit error rate. The proposed test methodology addresses these problems by simplifying the test stimulus application and test response capture/analysis procedures. In addition, the number of test hardware configurations needed to measure all the performance specifications is minimized and fewer as well as shorter tests are used to determine all the test specification values of interest. Test accuracy is achieved by optimizing the test stimulus so that the observed response has strong statistical correlation with the target test specification values. Experimental results show significant testing time reduction and was validated on 1.575 GHz and 900 MHz wireless transceiver prototypes.