A fully parallel VLSI implementation of distributed arithmetic
Weiqi Li, James B. Burr, A. M. Peterson · 2003
A novel architecture to implement distributed arithmetic in VLSI is presented. This architecture comprises a serial-in random-out multiport memory and a multi-input adder. The design of a 1.25- mu m CMOS convolution processor chip based on the architecture is reported. Issues in the development of chip architecture and design tools are discussed.>