A high performance RNS multiply-accumulate unit
A.P. Preethy, Damu Radhakrishnan, Amos R. Omondi · 2001
This paper discusses the VLSI implementation of a new architecture for a multiply-accumulate unit based on Residue Number System (RNS). The architecture and VLSI implementation of an arbitrary-moduli RNS MAC are given. The cost and performance are analyzed with respect to other designs, and the analysis indicates that the design is generally quite competitive. 1.