Overlapped subarray testing for wafer scale integration
Miroslaw Malek, Earl E. Swartzlander · 2003
A testing technique for wafer-scale integration arrays is introduced. It guarantees a high-fault coverage without specific requirements on design for testability. The technique is based on overlapped subarray testing and is capable of covering the vast majority of fault types including pattern sensitivity. Formulas giving the number of subarrays that must be tested for arbitrary array and partition sizes are derived. An example of testing a VLSI multiplier (which demonstrated pattern sensitivity faults) is given.>