Low latency elliptic curve cryptography accelerators for NISTcurves over binary fields
Chang Shu, Kris Gaj, Tarek A. El-Ghazawi · 2006
We designed hardware accelerators based on Xilinx FPGAs, XCV2000E, to speed up the scalar multiplications on elliptic curves recommended by NIST, over GF(2/sup 163/) and GF(2/sup 266/), in polynomial basis representation. Linear-feedback-shift-registers (LFSRs) are exploited in the most significant digit-serial (MSD) multipliers in order to improve design efficiency. We adopt the algorithm of scalar multiplication devised by Lopez and Dahab (1999). We demonstrate how this algorithm can be implemented using multiple multipliers working in parallel, and we select the optimal parameters for these multipliers. The accelerators can run around 3 times faster than the best hardware implementation reported previously by Gura et al. (2003) at CHES 2002, when ported to the same device Xilinx Virtex XC2000E.