LOW OVERHEAD BUILT-IN TESTABLE ERROR DETECTION AND CORRECTION WITH EXCELLENT FAULT COVERAGE
Mehdi Katoozi, A.W. Nordsieck · 2005
A method for the design of built-in testable (BIT) error detection and correction (EDAC) circuits is presented reducing test hardware by >50%. A lp CMOS, 16-bit EDAC designed and fabricated with this technique exhibits >99% fault coverage in 10 p at 25 MHz. Built-in test impacts the speed performance by only one gate delay regardless of the size of the EDAC. Various faults are injected into the chip to verifr the effectiveness of built-in test.