Module selection and data format conversion for cost-optimal DSP synthesis
Kazuhito Ito, L.E. Lucke, Keshab K. Parhi · 1994
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear programming (ILP) models which generate a blocked schedule for a DFG with implicit retiming, pipelining, and unfolding while performing module selection and data format conversion. A blocked schedule is a schedule which overlaps multiple iterations of the DFG to guarantee a minimum number of processors. Component modules are selected from a library of processors to minimize cost. Furthermore, we include data format converters between processors of different data formats. In addition, we minimize the unfolding factor of the blocked schedule. 1 Introduction In high-level synthesis a synchronous data-flow graph (DFG) is mapped onto a set of modules, registers, and interconnections [1]. An example of a DFG is shown in Fig. 1. The data-flow graph represents an iterative algorithm such as a digital signal processing...