A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder
M. Suzuoki, K. Kutaragi, T. Hiroi, Hidetaka Magoshi, Satoru Okamoto, M. Oka, Akio Ohba, Yasuyuki Yamamoto, M. Furuhashi, Masamitsu Tanaka, T. Yutaka, T. Okada, Masato Nagamatsu, Yukihiro Urakawa, M. Funyu, Atsushi Kunimatsu, Hiroaki Goto, K. Hashimoto, N. Ide, Hiroaki Murakami · IEEE Journal of Solid-State Circuits · 1999
A 250-MHz microprocessor intended for home computer entertainment consists of a CPU core with 128-b multimedia extensions, two single-instruction, multiple-data (SIMD) very long instruction word (VLIW) vector processors containing ten floating-point multiplier accelerators and four floating-point dividers, an MPEG-2 decoder, a ten-channel direct memory access (DMA) controller, and other peripherals with 128 b internal buses on one die. The core is a two-way superscalar MIPS-compatible microprocessor with 16-kB scratch-pad RAM. Each vector processor is a five-way SIMD-VLIW architecture, which is tightly dedicated for specific applications concerning three-dimensional geometry calculation and physical simulation. A DMA controller connects between main memory and each processor's local memory to conceal memory access penalty. It contains 10.5 M transistors in 17/spl times/14.1 mm and dissipates 15 W at 1.8 V.