Built-in self-test for analog-to-digital converters in SoC applications
Jason Wibbenmeyer, C.-I.H. Chen · 2005
This paper presents a built-in self-test (BIST) architecture for testing high speed analog-to-digital converters (ADCs) with sampling rates in excess of 1 GHz. A methodology for performing mixed-mode BIST simulations in SoC applications is proposed along with hardware for performing on-chip BIST. The architecture presented utilizes an on-chip ROM and allows for the generation of test signals with single frequency as well as multiple frequencies signals. The issues associated with BIST signal generation for low voltage ADCs are also discussed. Simulations revealed that the SFDR of the sinusoidal signal generated from the BIST hardware was 25.28 dB with a frequency of 312.5 MHz and 19.88 dB with a frequency of 416.67 MHz.