Cost-performance analysis of FPGA, VLSI and WSI implementations of a RAM-based neural network
Paul Morgan, Alistair Ferguson, Hamid Bolouri · 2002
The paper analyses the hardware implementation of a probabilistic RAM based neural network architecture, named HyperNet in terms of system training speed, size, and component cost. All the systems presented include on-board reinforcement training logic and the necessary control and interface circuitry. Circuit area, gate count, and speed figures are extrapolated from a 10,240 neuron custom VLSI based system constructed at the University of Hertfordshire in 1993. Varying degrees of parallelism, and three implementation technologies are considered. A palm-sized system with a single Xilinx 4025 FPGA serial processor can deliver approximately 800 times the performance of a Sun SPARCstation 10 at a cost of less than #1000. A double Eurocard sized custom VLSI based fully parallel system costs of the order of #10K and offers over five orders of magnitude training speed improvement over a Sun SPARCstation 10.