An HDTV video coder IC for ATV receivers
O. Duardo, Shining Hsieh, L. Wu, Jun‐Ho Boo, A. Khurjekar, R. Hingorani, Paul A. Wilford, Bob Bolton, H. Morinaka, Keisuke Okada, S. Hosotani, Tadashi Sumi, P. DaGraca, H. Yamamoto, T.C. Poon · IEEE Transactions on Consumer Electronics · 1997
An HDTV video decoder IC for ATV receivers is presented. Its dual decoder architecture supports MPEG-2 MP@HL (62,668,800 display samples per second) and an SDRAM memory bandwidth of 6.5 gigabits per second.