A reconfigurable design-for-debug infrastructure for SoCs
M. Abramovici, Paul D. Bradley, Kumar Dwarakanath, Peter L. Levin, Gérard Memmi, Dave Miller · 2006
In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port. The platform can be repeatedly reused to configure many debug structures such as assertions checkers, transaction identifiers, triggers, and event counters.